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Impact of the Device Size and N-type Isolation Layer Voltage on the Negative Input Withstand Capability of Fully Isolated nLDMOS

Q4 Engineering
IEEJ Transactions on Electronics, Information and Systems Pub Date : 2024-03-01 DOI:10.1541/ieejeiss.144.217
Atsushi Sakai, Katsumi Eikyu, Yotaro Goto, E. Tsukuda, Tamotsu Ogata
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器件尺寸和 N 型隔离层电压对全隔离 nLDMOS 负输入耐压能力的影响
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来源期刊
IEEJ Transactions on Electronics, Information and Systems
IEEJ Transactions on Electronics, Information and Systems Engineering-Electrical and Electronic Engineering
CiteScore
0.40
自引率
0.00%
发文量
200
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