DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS

IF 3.1 4区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Linus Y. Wong, Jialiang Zhang, Jing (Jane) Li
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引用次数: 0

Abstract

Rapid growth in data size poses significant computational and memory challenges to data processing. FPGA accelerators and near-storage processing have emerged as compelling solutions for tackling the growing computational and memory requirements. Many FPGA-based accelerators have shown to be effective in processing large data sets by leveraging the storage capability of either host-attached or FPGA-attached storage devices. However, the current HLS development environment does not allow direct access to host- or FPGA-attached NVMe storage from the HLS code. As such, users must frequently hand off between HLS and host code to access data in storage, and such a process requires tedious programming to ensure functional correctness. Moreover, since the HLS code uses radically different methods to access storage compared to DRAM, the HLS codebase targeting DRAM-based platforms cannot be easily ported to NVMe-based platforms, resulting in limited code portability and reusability. Furthermore, frequent suspension of HLS kernel and synchronization between CPU and FPGA introduce significant latency overhead and require sophisticated scheduling mechanisms to hide latency.

To address these challenges, we propose a new HLS storage interface named DONGLE 2.0 that enables direct FPGA-orchestrated NVMe storage access. By providing a unified interface for storage and memory access, DONGLE 2.0 allows a single-source HLS program to target multiple memory/storage devices, thus making the codebase cleaner, portable, and more efficient. DONGLE 2.0 is an extension to DONGLE 1.0 [1] but adds support for host-attached storage. While its primary focus is still on FPGA NVMe access in near-storage configurations, the added host storage support ensures its compatibility with platforms that lack native support for FPGA-attached NVMe storage. We implemented a prototype of DONGLE 2.0 using an AMD/Xilinx Alveo U200 FPGA and Solidigm DC-P4610 SSD. Our evaluation on various workloads showed a geometric mean speed-up of 2.3 × and a reduction in lines of code by 2.4 × compared to the state-of-the-art commercial platform when using FPGA-attached NVMe storage. Moreover, DONGLE 2.0 demonstrated a geometric mean speed-up of 1.5 × and a reduction in lines of code by 2.4 × compared to the state-of-the-art commercial platform when using host-attached NVMe storage.

DONGLE 2.0:面向 HLS 的 FPGA 直接协调 NVMe 存储
数据规模的快速增长给数据处理带来了巨大的计算和内存挑战。FPGA 加速器和近存储处理已成为应对不断增长的计算和内存需求的引人注目的解决方案。许多基于 FPGA 的加速器通过利用主机连接或 FPGA 连接存储设备的存储能力,在处理大型数据集方面表现出很好的效果。然而,当前的 HLS 开发环境不允许 HLS 代码直接访问主机或 FPGA 附加 NVMe 存储。因此,用户必须经常在 HLS 和主机代码之间切换,才能访问存储中的数据,而这一过程需要繁琐的编程来确保功能的正确性。此外,由于 HLS 代码使用的存储访问方法与 DRAM 截然不同,因此基于 DRAM 平台的 HLS 代码库无法轻松移植到基于 NVMe 的平台,导致代码的可移植性和可重用性受到限制。此外,HLS 内核的频繁暂停以及 CPU 和 FPGA 之间的同步会带来巨大的延迟开销,需要复杂的调度机制来隐藏延迟。为了应对这些挑战,我们提出了一种名为 DONGLE 2.0 的新型 HLS 存储接口,它可以实现直接的 FPGA 协调 NVMe 存储访问。通过为存储和内存访问提供统一接口,DONGLE 2.0 允许单源 HLS 程序针对多个内存/存储设备,从而使代码库更加简洁、可移植和高效。DONGLE 2.0 是对 DONGLE 1.0 [1] 的扩展,但增加了对主机附加存储的支持。虽然它的主要重点仍然是近存储配置中的 FPGA NVMe 访问,但新增的主机存储支持确保了它与缺乏 FPGA 附加 NVMe 存储原生支持的平台的兼容性。我们使用 AMD/Xilinx Alveo U200 FPGA 和 Solidigm DC-P4610 SSD 实现了 DONGLE 2.0 的原型。我们对各种工作负载进行的评估显示,在使用 FPGA 附加 NVMe 存储时,与最先进的商业平台相比,几何平均速度提高了 2.3 倍,代码行数减少了 2.4 倍。此外,与最先进的商业平台相比,DONGLE 2.0 在使用主机连接的 NVMe 存储时的几何平均速度提高了 1.5 倍,代码行数减少了 2.4 倍。
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来源期刊
ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.90
自引率
8.70%
发文量
79
审稿时长
>12 weeks
期刊介绍: TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.
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