Design-for-testability for reversible logic circuits based on bit-swapping

Abstract

The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ≥ 1. While analysing testability issues in a reversible circuit, the missing-gate fault model is often used for modelling physical defects in k-CNOT gates. A new design-for-testability (DFT) technique is proposed for reversible circuits that deploys bit-swapping using Fredkin reversible gates. It is shown that in an (n × n) circuit implemented with k-CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of maximum size 2n + 1 that detects all detectable missing gate faults in the original circuit, where n is the number of input/output lines in the circuit. The DFT overhead in terms of quantum cost is much less compared to that of previous approaches. The method is more advantageous for large circuits.