{"title":"RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks","authors":"Jaspinder Kaur, Shirshendu Das","doi":"10.1145/3637222","DOIUrl":null,"url":null,"abstract":"<p>Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with shared nature of cache to leak the secret information. The side channel and covert channel are the two well-known cache timing channel attacks. In this paper, we propose, Restricted Static Pseudo-Partitioning (RSPP), an effective partition based mitigation mechanisms that restricts the cache access of only the adversaries involved in the attack. It has an insignificant impact of only 1% in performance, as the benign process have access to full cache and restrictions are limited only to the suspicious processes and cache sets. It can be implemented with a maximum storage overhead of 1.45% of the total LLC size. This paper presents three variations of the proposed attack mitigation mechanism: RSPP, simplified-RSPP (S-RSPP) and core wise-RSPP (C-RSPP) with different hardware overheads. A full system simulator is used for evaluating the performance impact of RSPP. A detailed experimental analysis with different LLC and attack parameters is also discussed in the paper. RSPP is also compared with the existing defense mechanisms effective against cross-core covert channel attacks.</p>","PeriodicalId":50944,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2023-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Transactions on Design Automation of Electronic Systems","FirstCategoryId":"94","ListUrlMain":"https://doi.org/10.1145/3637222","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with shared nature of cache to leak the secret information. The side channel and covert channel are the two well-known cache timing channel attacks. In this paper, we propose, Restricted Static Pseudo-Partitioning (RSPP), an effective partition based mitigation mechanisms that restricts the cache access of only the adversaries involved in the attack. It has an insignificant impact of only 1% in performance, as the benign process have access to full cache and restrictions are limited only to the suspicious processes and cache sets. It can be implemented with a maximum storage overhead of 1.45% of the total LLC size. This paper presents three variations of the proposed attack mitigation mechanism: RSPP, simplified-RSPP (S-RSPP) and core wise-RSPP (C-RSPP) with different hardware overheads. A full system simulator is used for evaluating the performance impact of RSPP. A detailed experimental analysis with different LLC and attack parameters is also discussed in the paper. RSPP is also compared with the existing defense mechanisms effective against cross-core covert channel attacks.
期刊介绍:
TODAES is a premier ACM journal in design and automation of electronic systems. It publishes innovative work documenting significant research and development advances on the specification, design, analysis, simulation, testing, and evaluation of electronic systems, emphasizing a computer science/engineering orientation. Both theoretical analysis and practical solutions are welcome.