A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process

Abstract

In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature data. Halo-implanted channel transistors have a steeper and less distorted voltage characteristic curve compared to uniformly doped channel ones, which makes them a more appropriate option when designing asynchronous digital integrated circuits aimed at low bias and low power. Three gate models were created using weak inversion and pull-up and pull-down networks made with halo-implanted transistors. The results of the study and simulation of the three inverter digital gate topologies showed that the NOT inverter model, as expected, had a higher frequency than the NAND and NOR inverter models. The ring oscillators made with the NOT inverter came up with an 8.25-MHz switching frequency as well as a dynamic power close to 270 nW. A comparison with other ring oscillators from previous studies is also shown.