发布求助
文献互助 智能选刊 最新文献

Design of high speed and low power multiplier using dual-mode square adder

IF 0.6 Q3 Engineering
International Journal of Signal and Imaging Systems Engineering Pub Date : 2023-01-01 DOI:10.1504/ijsise.2023.133653
B. Jaya Lakshmi, R. Ramana Reddy, Naresh K. Darimireddy
{"title":"Design of high speed and low power multiplier using dual-mode square adder","authors":"B. Jaya Lakshmi, R. Ramana Reddy, Naresh K. Darimireddy","doi":"10.1504/ijsise.2023.133653","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":56359,"journal":{"name":"International Journal of Signal and Imaging Systems Engineering","volume":"104 1","pages":"0"},"PeriodicalIF":0.6000,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Signal and Imaging Systems Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1504/ijsise.2023.133653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0
分享
查看原文 本刊更多论文
采用双模平方加法器设计高速低功耗乘法器
本文章由计算机程序翻译，如有差异，请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
International Journal of Signal and Imaging Systems Engineering
International Journal of Signal and Imaging Systems Engineering ENGINEERING, ELECTRICAL & ELECTRONIC-
CiteScore
2.10
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信