Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

IF 0.5 Q4 TELECOMMUNICATIONS
D. S. Shylu Sam, P. Sam Paul, Diana Jeba Jingle, P. Mano Paul, Judith Samuel, J. Reshma, P. Sarah Sudeepa, G. Evangeline
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引用次数: 0

Abstract

— This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
基于多路复用编码器的90nm CMOS低功耗4位Flash ADC设计
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来源期刊
CiteScore
1.50
自引率
14.30%
发文量
0
审稿时长
12 weeks
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