Evaluation of dual-ONOFIC method for subthreshold leakage Reduction in domino circuit

IF 1.1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Vijay Kumar Magraiya, Tarun Kumar Gupta, Rajesh Verma, Amit Kumar Pandey, Shiv Prasad Kori
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引用次数: 0

Abstract

ABSTRACTA novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.KEYWORDS: DominoFinFETLECTORpull-uppull-downONOFICTemperatureDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Conflict of InterestThe authors declare that there is no conflict of interest regarding the publication of this paper.Author ContributionAll authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content; and have given final approval of the version to be published. Each author has participated sufficiently in the work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.The data and material are available within the manuscript.Compliance with ethical standardsThe authors declare that all procedures followed were in accordance with the ethical standards.Consent to participateAll the authors declare their consent to participate in this research article.Consent for PublicationAll the authors declare their consent for publication of the article on acceptance.Additional informationFundingThe author(s) reported there is no funding associated with the work featured in this article.
双onofic方法在减少多米诺电路阈下漏电中的应用评价
提出了一种新的双开/关逻辑(ONOFIC)下拉方法,以降低32 nm技术节点FinFET多米诺电路宽或门的亚阈值泄漏电流。一个ONOFIC块被插入到动态和倒立块的下拉网络中。采用32 nm BISM4模型的HSPICE模拟器对所提出的工作进行了仿真。CLIL(时钟低,输入低)状态的结果在降低低温和高温下的亚阈值泄漏电流方面是最有效的。采用该方法的OR2、OR4、OR8和OR16电路在低功耗(LP)模式下,与时钟高输入低的LECTOR多米诺骨牌门相比,可将亚阈值泄漏功耗降低48.1%,在短门(SG)模式下,可将亚阈值泄漏功耗降低74%。由于在低温和高温下,当所有输入都较低时,亚阈值电流较低,因此所提出的双ONOFIC下拉技术在LP模式下优于ONOFIC上拉技术。当低温和高温下输入高时,ONOFIC上拉技术比双ONOFIC下拉技术性能更好。免责声明作为对作者和研究人员的服务,我们提供此版本的已接受手稿(AM)。在最终出版版本记录(VoR)之前,将对该手稿进行编辑、排版和审查。在制作和印前,可能会发现可能影响内容的错误,所有适用于期刊的法律免责声明也与这些版本有关。利益冲突作者声明本文的发表不存在利益冲突。作者贡献所有作者都对数据的概念和设计、数据的获取或数据的分析和解释做出了重大贡献;曾参与手稿的起草或对重要的知识内容进行批判性修改;并最终批准了将要出版的版本。每个作者都充分参与了工作,对内容的适当部分承担公共责任。所有作者都阅读并批准了最终的手稿。数据和材料可在手稿中找到。符合道德标准作者声明所遵循的所有程序都符合道德标准。所有作者声明他们同意参与这篇研究文章。发表同意所有作者在接受时声明他们同意文章的发表。其他信息资金作者报告没有与本文所述工作相关的资金。
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来源期刊
International Journal of Electronics
International Journal of Electronics 工程技术-工程:电子与电气
CiteScore
3.30
自引率
15.40%
发文量
110
审稿时长
8 months
期刊介绍: The International Journal of Electronics (IJE) supports technical applications and developing research at the cutting edge of electronics. Encompassing a broad range of electronic topics, we are a leading electronics journal dedicated to quickly sharing new concepts and developments the field of electronics.
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