Vijay Kumar Magraiya, Tarun Kumar Gupta, Rajesh Verma, Amit Kumar Pandey, Shiv Prasad Kori
{"title":"Evaluation of dual-ONOFIC method for subthreshold leakage Reduction in domino circuit","authors":"Vijay Kumar Magraiya, Tarun Kumar Gupta, Rajesh Verma, Amit Kumar Pandey, Shiv Prasad Kori","doi":"10.1080/00207217.2023.2278439","DOIUrl":null,"url":null,"abstract":"ABSTRACTA novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.KEYWORDS: DominoFinFETLECTORpull-uppull-downONOFICTemperatureDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Conflict of InterestThe authors declare that there is no conflict of interest regarding the publication of this paper.Author ContributionAll authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content; and have given final approval of the version to be published. Each author has participated sufficiently in the work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.The data and material are available within the manuscript.Compliance with ethical standardsThe authors declare that all procedures followed were in accordance with the ethical standards.Consent to participateAll the authors declare their consent to participate in this research article.Consent for PublicationAll the authors declare their consent for publication of the article on acceptance.Additional informationFundingThe author(s) reported there is no funding associated with the work featured in this article.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"45 S213","pages":"0"},"PeriodicalIF":1.1000,"publicationDate":"2023-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/00207217.2023.2278439","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
ABSTRACTA novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.KEYWORDS: DominoFinFETLECTORpull-uppull-downONOFICTemperatureDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Conflict of InterestThe authors declare that there is no conflict of interest regarding the publication of this paper.Author ContributionAll authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content; and have given final approval of the version to be published. Each author has participated sufficiently in the work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.The data and material are available within the manuscript.Compliance with ethical standardsThe authors declare that all procedures followed were in accordance with the ethical standards.Consent to participateAll the authors declare their consent to participate in this research article.Consent for PublicationAll the authors declare their consent for publication of the article on acceptance.Additional informationFundingThe author(s) reported there is no funding associated with the work featured in this article.
期刊介绍:
The International Journal of Electronics (IJE) supports technical applications and developing research at the cutting edge of electronics. Encompassing a broad range of electronic topics, we are a leading electronics journal dedicated to quickly sharing new concepts and developments the field of electronics.