{"title":"17 Level Hybrid Diode Clamped Inverter With Reduced Number of Components","authors":"Mohammed Alsumady, Ibrahim Jaber, Khalid Nusserat","doi":"10.37256/jeee.2220233266","DOIUrl":null,"url":null,"abstract":"Multilevel inverters (MLIs) are gaining more interest recently in medium to high power applications. The main problem with various MLI topologies is that they require a large number of switching devices and DC voltage sources while producing a small number of voltage levels. Which results in bulky inverters with high cost and high output voltage/current total harmonic distortion (THD). This paper introduces a new novel asymmetrical 17-level MLI design using two DC voltage sources and a reduced number of switches. This was achieved by combining a voltage summing and subtracting circuit with a modified diode clamped MLI (DC-MLI), which divides the voltage by two. Thus, generating more voltage levels. nearest level control (NLC) is used to produce the switching signals at a switching frequency of 50Hz. The design is tested and simulated using MATLAB/Simulink, the output voltage THD is kept around 5.7%. The obtained results are compared with other recent 17-level topologies, showing that a good improvement is achieved.","PeriodicalId":39047,"journal":{"name":"Journal of Electrical and Electronics Engineering","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electrical and Electronics Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.37256/jeee.2220233266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0
Abstract
Multilevel inverters (MLIs) are gaining more interest recently in medium to high power applications. The main problem with various MLI topologies is that they require a large number of switching devices and DC voltage sources while producing a small number of voltage levels. Which results in bulky inverters with high cost and high output voltage/current total harmonic distortion (THD). This paper introduces a new novel asymmetrical 17-level MLI design using two DC voltage sources and a reduced number of switches. This was achieved by combining a voltage summing and subtracting circuit with a modified diode clamped MLI (DC-MLI), which divides the voltage by two. Thus, generating more voltage levels. nearest level control (NLC) is used to produce the switching signals at a switching frequency of 50Hz. The design is tested and simulated using MATLAB/Simulink, the output voltage THD is kept around 5.7%. The obtained results are compared with other recent 17-level topologies, showing that a good improvement is achieved.
期刊介绍:
Journal of Electrical and Electronics Engineering is a scientific interdisciplinary, application-oriented publication that offer to the researchers and to the PhD students the possibility to disseminate their novel and original scientific and research contributions in the field of electrical and electronics engineering. The articles are reviewed by professionals and the selection of the papers is based only on the quality of their content and following the next criteria: the papers presents the research results of the authors, the papers / the content of the papers have not been submitted or published elsewhere, the paper must be written in English, as well as the fact that the papers should include in the reference list papers already published in recent years in the Journal of Electrical and Electronics Engineering that present similar research results. The topics and instructions for authors of this journal can be found to the appropiate sections.