17 Level Hybrid Diode Clamped Inverter With Reduced Number of Components

Q4 Engineering
Mohammed Alsumady, Ibrahim Jaber, Khalid Nusserat
{"title":"17 Level Hybrid Diode Clamped Inverter With Reduced Number of Components","authors":"Mohammed Alsumady, Ibrahim Jaber, Khalid Nusserat","doi":"10.37256/jeee.2220233266","DOIUrl":null,"url":null,"abstract":"Multilevel inverters (MLIs) are gaining more interest recently in medium to high power applications. The main problem with various MLI topologies is that they require a large number of switching devices and DC voltage sources while producing a small number of voltage levels. Which results in bulky inverters with high cost and high output voltage/current total harmonic distortion (THD). This paper introduces a new novel asymmetrical 17-level MLI design using two DC voltage sources and a reduced number of switches. This was achieved by combining a voltage summing and subtracting circuit with a modified diode clamped MLI (DC-MLI), which divides the voltage by two. Thus, generating more voltage levels. nearest level control (NLC) is used to produce the switching signals at a switching frequency of 50Hz. The design is tested and simulated using MATLAB/Simulink, the output voltage THD is kept around 5.7%. The obtained results are compared with other recent 17-level topologies, showing that a good improvement is achieved.","PeriodicalId":39047,"journal":{"name":"Journal of Electrical and Electronics Engineering","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electrical and Electronics Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.37256/jeee.2220233266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0

Abstract

Multilevel inverters (MLIs) are gaining more interest recently in medium to high power applications. The main problem with various MLI topologies is that they require a large number of switching devices and DC voltage sources while producing a small number of voltage levels. Which results in bulky inverters with high cost and high output voltage/current total harmonic distortion (THD). This paper introduces a new novel asymmetrical 17-level MLI design using two DC voltage sources and a reduced number of switches. This was achieved by combining a voltage summing and subtracting circuit with a modified diode clamped MLI (DC-MLI), which divides the voltage by two. Thus, generating more voltage levels. nearest level control (NLC) is used to produce the switching signals at a switching frequency of 50Hz. The design is tested and simulated using MATLAB/Simulink, the output voltage THD is kept around 5.7%. The obtained results are compared with other recent 17-level topologies, showing that a good improvement is achieved.
减少元件数量的17电平混合二极管箝位逆变器
近年来,多电平逆变器(mli)在中高功率应用中获得了越来越多的关注。各种MLI拓扑的主要问题是,它们需要大量的开关器件和直流电压源,而产生的电压电平却很少。这导致逆变器体积庞大,成本高,输出电压/电流总谐波失真(THD)高。本文介绍了一种采用两个直流电压源和减少开关数量的新型非对称17电平MLI设计。这是通过将电压加和减电路与改进的二极管箝位MLI (DC-MLI)相结合实现的,该电路将电压除以2。因此,产生更多的电压水平。最近电平控制(NLC)用于产生开关频率为50Hz的开关信号。利用MATLAB/Simulink对设计进行了测试和仿真,输出电压THD保持在5.7%左右。将得到的结果与其他最近的17层拓扑进行了比较,表明取得了很好的改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
Journal of Electrical and Electronics Engineering
Journal of Electrical and Electronics Engineering Engineering-Electrical and Electronic Engineering
CiteScore
0.90
自引率
0.00%
发文量
0
审稿时长
16 weeks
期刊介绍: Journal of Electrical and Electronics Engineering is a scientific interdisciplinary, application-oriented publication that offer to the researchers and to the PhD students the possibility to disseminate their novel and original scientific and research contributions in the field of electrical and electronics engineering. The articles are reviewed by professionals and the selection of the papers is based only on the quality of their content and following the next criteria: the papers presents the research results of the authors, the papers / the content of the papers have not been submitted or published elsewhere, the paper must be written in English, as well as the fact that the papers should include in the reference list papers already published in recent years in the Journal of Electrical and Electronics Engineering that present similar research results. The topics and instructions for authors of this journal can be found to the appropiate sections.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信