Design Synthesis and Performance Measurement of Pipelined Flash ADC for SoC Applications

Abstract

This paper presents a design synthesis and performance measurement of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC in 130 nanometer CMOS. CMOS technology has superior performance of sampling rate of 2.5 GHz for input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC