Influence of damping and voltage dependent leakage resistance on mid-frequency power noise

Abstract

Accurate predictions of power/ground-noise are essential for adequate chip and package design. This paper studies especially the influence of damping and leakage on the mid-frequency power noise caused by switching activity variations of logic circuits. The noise is determined by simulations and calculated by a closed form expression which is derived for a simplified 2D circuit representation of the chip and package power delivery network. Both approaches agree within 16%. The voltage dependency of the leakage resistance is found to be essential for the power noise when the noise is determined by the resonance between on-die capacitors and the next stage of decoupling capacitors. It is shown that damping and leakage reduce significantly the influence of the on-die decoupling capacitance and package capacitor inductance on the mid-frequency power noise.