J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela
{"title":"Design and fabrication of new high voltage current limiting devices for serial protection applications","authors":"J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela","doi":"10.1109/ISPSD.1996.509481","DOIUrl":null,"url":null,"abstract":"This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of \"functional integration\", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1996.509481","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of "functional integration", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.