{"title":"Exact closed form formula for partial mutual inductances of on-chip interconnects","authors":"Guoan Zhong, Cheng-Kok Koh","doi":"10.1109/ICCD.2002.1106807","DOIUrl":null,"url":null,"abstract":"In this paper we propose a new exact closed form mutual inductance equation for on-chip interconnects. We express the mutual inductance between two parallel rectangular conductors as a weighted sum of self-inductances. We do not place any restrictions on the alignment of the two parallel rectangular conductors. Moreover they could be co-planar or reside on different layers. Most important, experimental results show that our formula is numerically more stable than that derived by Hoer and Love (1965) for long parallel onchip interconnects.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2002.1106807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 31
Abstract
In this paper we propose a new exact closed form mutual inductance equation for on-chip interconnects. We express the mutual inductance between two parallel rectangular conductors as a weighted sum of self-inductances. We do not place any restrictions on the alignment of the two parallel rectangular conductors. Moreover they could be co-planar or reside on different layers. Most important, experimental results show that our formula is numerically more stable than that derived by Hoer and Love (1965) for long parallel onchip interconnects.