Express Circuit Switching: Improving the Performance of Bufferless Networks-on-Chip

Abstract

In this paper, we propose a new scheme for packet-switched bufferless Networks-on-Chip (NoCs). The goal is to reduce the area and power consumption while providing high performance. In the proposed scheme, we develop a new bufferless routing algorithm. Extensive cycle-accurate simulations have been conducted to show that the proposed scheme delivers a superior performance compared to both traditional buffered and bufferless methods.