Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS)

Abstract

In this paper, two novel hybrid adder designs, namely, FHAS-1 and FHAS-2 have been proposed. These designs are designed using multiplexor, XOR and XNOR gates and they can be operated as both adder and subtractor modules effectively. A hybrid logic design principle has been utilized to construct the circuit structures. Transmission gate structures have been employed to realize the multiplexor design which determines whether addition or subtraction operation has to be performed by circuit. These circuits are designed using BSIMCMG FinFET 32nm technology files and the simulation is carried out using Cadence® Virtuoso tool. It is demonstrated that the proposed circuits incur lower power consumption and reduced delay compared to existing adder and subtractor circuit counterparts. Proposed circuits have been analyzed in terms of varying load and changing supply voltage conditions and the efficiency of FHAS-1 and FHAS-2 have been validated. It is observed that proposed FHAS-1 circuit is 81.25%, 42.13%, 25% and 13% more power efficient than the hybrid full adder circuit counterparts such as HFA -19T, HFA -22T, HFA -26T and HFA -17T, respectively.