A 0.23V 40nm OAI-ROM with Low Active and Standby Power for AI-based IoT Edge Devices

Abstract

Sub-threshold (sub-Vt) ROM is the code storage element in AI-based IoT devices, such as voice-activated edge-computing SoCs. Reducing standby power for longer battery life and improving operating speed for faster response are two design pursuits for sub-Vt ROM. A conventional NAND-ROM used an extra code-inversion-based flag-table for enhancing speed but sacrificing leakage. In this work, we propose OAI-ROM to improve speed without using the flag-table for leakage reduction. The proposed ROM adopts the interleaved-shielding scheme to avoid crosstalk and the adaptive leakage compensation to achieve variation-resilient sub-Vt operation. The 40nm OAI-ROM has a minimum supply voltage of 0.23V with 23% and 88% less active and standby power, respectively, and 1.67 times higher speed compared to the NAND-ROM redesigned in the same CMOS.