95 GHz down converting mixers in CMOS 65 nm technology

J. Elkind, E. Socher
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Abstract

This paper presents three single balanced down-converting mixer designs in CMOS 65 nm technology. The three designs operate at 95 GHz and reach a maximum conversion gain of 8, 6.9 and 10.2 dB respectively. Due to the use of single balanced topology, the designs occupy a relatively small core area of 0.89×0.51, 0.078×0.14 and 0.053×0.17 mm2 and their DC power consumption is only 26, 29 and 12.4 mW.
95 GHz下变频混频器在CMOS 65纳米技术
本文提出了三种基于CMOS 65纳米技术的单平衡下转换混频器设计。这三种设计的工作频率为95 GHz,最大转换增益分别为8、6.9和10.2 dB。由于采用单平衡拓扑,这些设计的核心面积相对较小,分别为0.89×0.51、0.078×0.14和0.053×0.17 mm2,直流功耗仅为26、29和12.4 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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