{"title":"An enhanced data rate chaos-based multilevel transceiver design exploiting ergodicity","authors":"D. Majumdar, Robin Moritz, H. Leung, J. Brent","doi":"10.1109/MILCOM.2010.5680115","DOIUrl":null,"url":null,"abstract":"Conventionally, practical chaos-based communication transceivers have failed to offer supportable data rates of the order of Mbps. The actual feasibility of such a high data rate chaos-based transceiver has been successfully addressed by exploiting the basics of Ergodic Theory. The proposed implementation is based on the Ergodic Chaotic Parameter Modulation (ECPM) scheme. However, the designed transceiver could only support a data rate of about 1–2 Mbps. Therefore, in order to address real-time applications with data rate requirements of the order of tens of Mbps, the supportable data rate of the practical transceiver needed enhancement. The issue of further increasing the data rate has been addressed by using multilevel Quadrature Amplitude Modulation (QAM) together with the basics of ECPM. Although, fundamentals of theoretical evaluation proposed the possibility of a M-level QAM-ECPM transceiver, the actual feasibility of such a transceiver still remained ambiguous. A primary factor contributing to this lack of feasibility is the need for practically viable solutions of suitable chaotic maps that can support multilevel schemes. This paper presents the design and implementation of a practical multilevel ECPM transceiver with data rate of the order of 48 Mbps. Theoretical as well as practically achievable data rates have also been estimated. Design of suitable chaotic maps required to make the proposed transceiver a reality has also been addressed. Power efficiency and resource usage of the designed prototype has been evaluated based on both Altera Stratix FPGA implementation as well as silicon.","PeriodicalId":330937,"journal":{"name":"2010 - MILCOM 2010 MILITARY COMMUNICATIONS CONFERENCE","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 - MILCOM 2010 MILITARY COMMUNICATIONS CONFERENCE","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MILCOM.2010.5680115","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Conventionally, practical chaos-based communication transceivers have failed to offer supportable data rates of the order of Mbps. The actual feasibility of such a high data rate chaos-based transceiver has been successfully addressed by exploiting the basics of Ergodic Theory. The proposed implementation is based on the Ergodic Chaotic Parameter Modulation (ECPM) scheme. However, the designed transceiver could only support a data rate of about 1–2 Mbps. Therefore, in order to address real-time applications with data rate requirements of the order of tens of Mbps, the supportable data rate of the practical transceiver needed enhancement. The issue of further increasing the data rate has been addressed by using multilevel Quadrature Amplitude Modulation (QAM) together with the basics of ECPM. Although, fundamentals of theoretical evaluation proposed the possibility of a M-level QAM-ECPM transceiver, the actual feasibility of such a transceiver still remained ambiguous. A primary factor contributing to this lack of feasibility is the need for practically viable solutions of suitable chaotic maps that can support multilevel schemes. This paper presents the design and implementation of a practical multilevel ECPM transceiver with data rate of the order of 48 Mbps. Theoretical as well as practically achievable data rates have also been estimated. Design of suitable chaotic maps required to make the proposed transceiver a reality has also been addressed. Power efficiency and resource usage of the designed prototype has been evaluated based on both Altera Stratix FPGA implementation as well as silicon.