A novel compact architecture for a programmable full-range CNN in 0.5 /spl mu/m CMOS technology

Abstract

Describes an analogue hardware implementation of a programmable full-range CNN. The used technology is the MIETEC 0.5 /spl mu/m CMOS process. The most important building blocks in each cell are its multipliers and an integrator with a hard-limited output. For the multipliers it is shown that the application of 2-quadrant types suffices, without loss of generality of the resulting network. As the number of multipliers per cell can be quite large, this means an important reduction of the circuit complexity. The integrator is implemented as a single capacitor. Hard-limiting is incorporated by a small clamper circuit. The resulting low-power and low-voltage circuit stands out for its low number of components and dense implementation. Its usefulness is illustrated with simulation results of this CNN used as a connected component detector.