Hybrid fault simulation with compiled and event-driven methods

Abstract

In this paper, we propose a method to speed-up fault simulation. The proposed method takes a hybrid approach with compiled simulation and event-driven simulation. Compiled simulation is applied for fan-out free regions (FFRs). FFRs to be simulated are selected with the event-driven manner. Since the event-driven simulation contributes to avoidance of waste simulation and the compiled simulation contributes to reduction of memory access, the proposed method can reduce the simulation time effectively. Note that this work targets on combinational circuits or a full-scan sequential circuit, and the single stuck-at fault model is assumed. Experimental results for benchmark circuits show that the proposed method could reduce runtime in half compared with concurrent (event-driven) fault simulation