Dual-Core Architecture for Dynamic Binary Translation System: Tradeoff between Frequency and Bandwidth

Abstract

Traditional DBT system is hard to accelerate by introducing a customized processor core because the startup overhead is hard to eliminate. In this paper, we concentrate on how to choose a suitable layout of the DBT core in a dual-core system. We analyze the tradeoff between the frequency and the memory bandwidth of the DBT core through an analytical model, and simulated 4 different and usual layouts of dual-core DBT in experiments. Finally, the validation of our model is verified through experimental results: the dual-core DBT framework can sharply reduce the startup overhead and speedup the translation-execution process by about 12%. Moreover, we also found the relationship between the code expand rate and the communication overhead: the performance of a program with high code expand rate is not sensitive to the communication speed of the platform.