Analog front end for DMT-based VDSL

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993065

W. De Wilde, N. Scantamburlo, M. Combe, J. Van Leeuwe, K. Doorakkers, Y. Mazoyer, C. Renous, R. Petigny, A. Bonin, B. Bayracki, B. Belhi, E. Moons, J. Sevenhans

引用次数: 12

Abstract

A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35/spl mu/m ASIC. When fully active, the ASIC dissipates 480mW at 3.3V supply, providing resolution equivalent to 12b without trimming.

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基于dmt的VDSL模拟前端

基于dmt的VDSL的12MHz 760mW模拟前端将除线路驱动器外的所有有源组件集成在单个BiCMOS 0.35/spl mu/m ASIC中。当完全激活时，ASIC在3.3V电源下耗散480mW，提供相当于12b的分辨率而不微调。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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