L. Grenouillet, P. Khare, J. Gimbert, M. Hargrove, M. Jaud, Q. Liu, Y. Le Tiec, R. Wacquez, N. Loubet, K. Cheng, S. Holmes, S. Liu, T. Hook, S. Teehan, J. Guilford, S. Schmitz, P. Kulkarni, J. Kuss, M. Terrizzi, S. Luning, B. Doris, M. Vinet
{"title":"Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide","authors":"L. Grenouillet, P. Khare, J. Gimbert, M. Hargrove, M. Jaud, Q. Liu, Y. Le Tiec, R. Wacquez, N. Loubet, K. Cheng, S. Holmes, S. Liu, T. Hook, S. Teehan, J. Guilford, S. Schmitz, P. Kulkarni, J. Kuss, M. Terrizzi, S. Luning, B. Doris, M. Vinet","doi":"10.1109/SOI.2012.6404363","DOIUrl":null,"url":null,"abstract":"Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International SOI Conference (SOI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2012.6404363","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.
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