Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies

Abstract

Heterogeneous 3D/2.5D stacking allows to tightly couple components that are ideally integrated into different technologies yielding advantages in nearly all design metrics. Massively parallel and scalable communication architectures between the components in such 3D ICs are commonly implemented through Networks-on-Chip (NoCs). This paper contributes a systematic approach to improve the efficiency of NoCs for these heterogeneous 3D ICs. The core idea is a heterogeneous co-design of the NoC routing algorithm and router micro-architecture. Thereby, the level of heterogeneity is derived from the physical implications of the different technologies. The proposed systematic approach enables a simultaneous improvement in the NoC power consumption, silicon footprint, and performance by 17 %, 45 %, and 52 %, respectively.