Evaluation of sSOI wafers for 22nm node and beyond

2012 IEEE International SOI Conference (SOI) Pub Date : 2012-10-01 DOI:10.1109/SOI.2012.6404397

F. Allibert, K. Cheng, M. Vinet, W. Schwarzenbach, A. Khakifirooz, L. Ecarnot, B. Nguyen, B. Doris

引用次数: 3

Abstract

We assessed the performance of planar fully-depleted transistors built on sSOI wafers by comparing them to devices fabricated with the same process on SOI. A 23% increase in device performance was demonstrated, while maintaining at least as good device electrostatics and matching as SOI.

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22nm及以上节点sSOI晶圆的评估

我们通过将sSOI晶圆上的平面全耗尽晶体管与在SOI晶圆上采用相同工艺制造的器件进行比较，评估了它们的性能。在保持至少与SOI一样好的设备静电和匹配的同时，设备性能提高了23%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2012 IEEE International SOI Conference (SOI)

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