Irregular-Program-Based Hash Algorithms

Abstract

Because of their energy efficiency over general-purpose central processing unit (CPU), application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) have been used to accelerate blockchain mining. These hardware accelerators create the concern of centralization because the ASIC devices are dominated by a few manufacturers. Several algorithms are proposed to lower the benefits of ASIC including memory-intensive hash algorithms, where the memory access patterns are random and depend on input data. To further lower the potential hardware acceleration, in this paper, we introduce irregular-program-based hash algorithms, where both the code path and memory access are random and depend on input data. We present an example of the hash algorithm based on dynamic search tree (DST), which exhibits both control-path and memory-access irregularities. We compare the performance of a CPU-based implementation of the DST to an existing FPGA-based implementation, which shows comparable performance. An instance of the proposed hash algorithm is elaborated, and the test inputs and outputs are given.