Memory-configuration and memory-bandwidth in the sliding-window (SW) switch architecture

Abstract

The key problem in a parallel system is how to distribute the work load to the components of the system in order to get optimal resource utilization, maximize throughput, and minimize response time. The sliding-window (SW) switch is a highly parallel architecture that uses an array of memory-modules to store and process data packets in high speed-networks and Internets. In this paper, we study two key aspects in the design of a high-speed router/switch using the SW switch architecture. The effect of the memory-configuration and the memory-bandwidth in the performance of the SW switch architecture is investigated under bursty-traffic conditions.