{"title":"VLSI implementation of a generic discrete transform processor for real-time applications","authors":"C. Chiu, K.H. Tsui","doi":"10.1109/APCCAS.1994.514528","DOIUrl":null,"url":null,"abstract":"A function-specific VLSI chip that can compute the discrete cosine, sine, Fourier, and Hartley transforms in a real-time manner is presented. A generic transform processor based on the transfer function approach for those discrete transforms is described. This processor is well suited for VLSI implementation because it is modular, regular, local connected and without ally limitation on transform size N. The VLSI implementation of the transform processor based on pipelined configurations is described. This realization of the processor using 0.8 /spl mu/m SPDM CMOS technology can achieve a 544 Mb/s data processing rate.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514528","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A function-specific VLSI chip that can compute the discrete cosine, sine, Fourier, and Hartley transforms in a real-time manner is presented. A generic transform processor based on the transfer function approach for those discrete transforms is described. This processor is well suited for VLSI implementation because it is modular, regular, local connected and without ally limitation on transform size N. The VLSI implementation of the transform processor based on pipelined configurations is described. This realization of the processor using 0.8 /spl mu/m SPDM CMOS technology can achieve a 544 Mb/s data processing rate.