An experimental distributed switching system to handle bursty computer traffic

Abstract

An experimental switching system has been built using commercially available integrated semiconductors to switch data. Data messages to be handled by the system may vary in bit rate (100 bits/sec - 4 × 106 bits/sec), message length, and rate of message occurrence. The system uses a synchronous transmission facility with a crystal stabilized clock rate of approximately 6 MHz. The signaling format chosen facilitates data interchange between a number of similar small sequential machines that share a common transmission facility. Efficient data transmission over common carrier systems requires a change in signal format at the channel inputs. Systems involving interconnected loops are discussed briefly; however, the traffic handling capacity of such systems must be analyzed to determine the memory requirements at the junction points. This paper is concerned primarily with the detailed organization of a single loop.