Clock and Data Recovery for 10-Gb/s EPON Application

Abstract

An integrated 10-Gb/s clock and data recovery circuit incorporates a LC-tank voltage-controlled oscillator, a half-rate binary phase detector and charge pump. On the basis of R.C.Walker's second-order model, and in accordance with jitter tolerance and jitter transfer, the minimum stability factor are derived in a view to determine the value of Cz and Rz finally. Accomplished circuit design in 0.13-um CMOS process, the power consumption is 210 mW from a supply voltage of 1.2V. When 10.125 Gb/s pseudorandom binary sequence is used, the jitter of the recovered clock is a peak-to- peak jitter of 8 ps.