TAN: a packet switched network for VLSI testing

Abstract

In this paper, we introduce the idea of using packet switched network as the mode of communication between automatic test equipment and the VLSI chip under test in a multisite ATE architecture. We show that our architecture, which we refer to as test area network reduces the complexity and time involved in testing tens of chips at a time. To increase the ATE utilization, we distribute a portion of ATE's task of signature verification to the intelligent test-heads, which are now capable of applying patterns and verifying signatures produced by the chip being tested. Our analysis and empirical results indicate a speed up of 4 to 10 by using existing network infrastructure.