Removing cell demultiplexing performance bottleneck in ATM pseudo wire emulation over MPLS networks

Puneet Konghot, Hao Che
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Abstract

Cell multiplexing is highly desirable to achieve increased transport efficiency in asynchronous transfer mode (ATM) pseudo wire emulation over a multiprotocol label switching (MPLS) network. However, supporting cell multiplexing can create performance bottleneck at the egress provider edge (PE) where fully programmable network processors are used to do the cell demultiplexing. In this paper, a scheme is proposed to allow a large number of cells to be demultiplexed, without having to implement special ASIC-based hardware optimized for cell demultiplexing. The idea is to configure concatenated data plane processing devices to share the cell demultiplexing task with the egress PE. Analysis shows that the use of just two processing devices is sufficient to achieve high transport efficiency. This may as well be achieved by the addition of one router without a central control card. Therefore, service providers can employ this scheme to enable cell multiplexing with limited add-on cost, while preserving the existing investment.
消除MPLS网络上ATM伪线仿真中的小区解复用性能瓶颈
在多协议标签交换(MPLS)网络上的异步传输模式(ATM)伪线仿真中,非常需要单元多路复用来实现更高的传输效率。然而,支持小区多路复用可能会在出口提供商边缘(PE)产生性能瓶颈,在PE中使用完全可编程的网络处理器来执行小区多路复用。本文提出了一种允许大量单元解复用的方案,而无需实现针对单元解复用进行优化的特殊基于asic的硬件。其思想是配置连接的数据平面处理设备,以便与出口PE共享单元解复用任务。分析表明,仅使用两台加工设备就足以达到较高的运输效率。这也可以通过增加一个没有中央控制卡的路由器来实现。因此,服务提供商可以使用该方案以有限的附加成本实现小区复用,同时保留现有投资。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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