Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors

Abstract

This paper presents a pre-silicon validation methodology of Intelreg Itaniumreg processor family (IPF) memory ordering for multi-core processors. The validation methodology includes a multi-core simulation environment, a shared memory multiprocessor reference model, memory ordering checkers, and a tightly combined strategy of stimulus and coverage, specifically developed for IPF memory ordering. The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-silicon validation stage