{"title":"A novel MICS chirp FSK receiver front-end","authors":"Mouna Bettaieb, H. Trabelsi, M. Masmoudi","doi":"10.1109/ICEMIS.2017.8272971","DOIUrl":null,"url":null,"abstract":"This paper presents a new receiver front-end for Chirp FSK MICS system dedicated to medical implantable devices. The receiver uses MICS band at 402–405 MHz. Chirped FSK pulses are used to encode the binary data. This enables non coherent FSK demodulator which simplifies the receiver architecture. The receiver is designed to communicate a maximum data rate of 100 Kbps. The various blocks parameters of the receiver are simulated and optimized to meet receiver specifications. The receiver realizes a sensitivity of −93 dBm, a voltage gain of 29 dB and a NF of 5.5 dB. Linearity is also evaluated and the receiver IIP3 is equal to −12.6 dBm. After the down conversion mixer, a variable bandwidth low pass filter, with 40–300 MHz control range, passes the desired channel signal while eliminating in-band interference and thus lowering the sensitivity of the receiver.","PeriodicalId":117908,"journal":{"name":"2017 International Conference on Engineering & MIS (ICEMIS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Engineering & MIS (ICEMIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEMIS.2017.8272971","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a new receiver front-end for Chirp FSK MICS system dedicated to medical implantable devices. The receiver uses MICS band at 402–405 MHz. Chirped FSK pulses are used to encode the binary data. This enables non coherent FSK demodulator which simplifies the receiver architecture. The receiver is designed to communicate a maximum data rate of 100 Kbps. The various blocks parameters of the receiver are simulated and optimized to meet receiver specifications. The receiver realizes a sensitivity of −93 dBm, a voltage gain of 29 dB and a NF of 5.5 dB. Linearity is also evaluated and the receiver IIP3 is equal to −12.6 dBm. After the down conversion mixer, a variable bandwidth low pass filter, with 40–300 MHz control range, passes the desired channel signal while eliminating in-band interference and thus lowering the sensitivity of the receiver.