A 0.2-3.3 GHz 2.4 dB NF 45 dB Gain Current-Mode Front-End for SAW-less Receivers in 180 nm CMOS

Abstract

A CMOS fully differential current-mode frontend for SAW-less receivers is proposed. The noise-cancelling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current-mode domain. The stacked nMOS/pMOS configurations improve their power efficiency. Traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides a NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The inband and out-of-band IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively.