Using Genetic Algorithm to Improve the Performance of Sigma-Delta Converter Used on Earthquake Monitoring Systems

O. Mohamed, R. Abdelrassoul, M. Mohanna, H. Nofal
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Abstract

An earthquake monitoring system consists of many electronic devices, one of this vital device is the digitizer which converts the analogue signal coming from the seismometer (sensor) to digital signal. The Digitizer consists of three main modules, the first module is front-end, the second module is the analog to digital converter using the oversampling technique with the decimation filter, finally the packetization module. This paper will focus on improving the performance of Sigma-delta converter which is used in the digitizer. Genetic algorithm will find the optimum coefficients value of cascaded integrators with distributed feedback Sigma-delta to maximize the signal to noise ratio and the effective number of bits. In addition, this paper will include the steps of choosing the best oversampling ratio and the best order of Sigma-delta. The final design will be implemented on an FPGA kit. As a result of this paper the third order sigma-delta is selected, and in addition, the signal to noise ratio and the effective number of bits are improved to 156 dB, 25.63 bits respectively. The operating frequency of the selected order sigma-delta is 125. 412MHz on FPGA kit.
用遗传算法改进地震监测系统中Sigma-Delta变换器的性能
地震监测系统由许多电子设备组成,其中一个重要的电子设备是数字化仪,它将地震检波器(传感器)发出的模拟信号转换为数字信号。数字化仪由三个主要模块组成,第一个模块是前端模块,第二个模块是采用过采样技术和抽取滤波器的模数转换器,最后是分组模块。本文将重点研究如何提高数字化仪中使用的σ - δ变换器的性能。遗传算法通过分布反馈Sigma-delta找出级联积分器的最优系数值,使信噪比和有效比特数最大化。此外,本文将包括选择最佳过采样比和最佳Sigma-delta阶数的步骤。最终设计将在FPGA套件上实现。由于本文选择了三阶σ - δ,并且将信噪比和有效比特数分别提高到156 dB和25.63 bits。所选阶σ - δ的工作频率为125。FPGA套件上的412MHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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