Customized architecture for implementing configurable FFT on FPGA

V. Chandrakanth, S. Tripathi
{"title":"Customized architecture for implementing configurable FFT on FPGA","authors":"V. Chandrakanth, S. Tripathi","doi":"10.1109/IADCC.2013.6514412","DOIUrl":null,"url":null,"abstract":"Fourier transform algorithm has encompassed diverse fields of engineering including specialized fields like radars, communications and image processing systems. Therefore there have been continual efforts to improve the efficiency of FFT implementation in real time systems and other hardware. To reduce design time and time to market, FPGA vendors have developed IP cores which can be readily used in our applications. But these IP core designs though efficient are highly abstract and do not provide the designer to modify them according to his requirement which leads to inefficient design realization. Vendor provided IP cores do not give access to FFT kernel matrix thus restricting the configurability and efficiency of using them. In this paper we have designed a customized architecture to perform FFT with access to twiddle factors for improved configurability. The designed architecture is further modified to perform variable point FFT targeted for application in multirate systems. The architecture designed is generic and can be implemented on any vendor platform.","PeriodicalId":325901,"journal":{"name":"2013 3rd IEEE International Advance Computing Conference (IACC)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 3rd IEEE International Advance Computing Conference (IACC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IADCC.2013.6514412","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

Fourier transform algorithm has encompassed diverse fields of engineering including specialized fields like radars, communications and image processing systems. Therefore there have been continual efforts to improve the efficiency of FFT implementation in real time systems and other hardware. To reduce design time and time to market, FPGA vendors have developed IP cores which can be readily used in our applications. But these IP core designs though efficient are highly abstract and do not provide the designer to modify them according to his requirement which leads to inefficient design realization. Vendor provided IP cores do not give access to FFT kernel matrix thus restricting the configurability and efficiency of using them. In this paper we have designed a customized architecture to perform FFT with access to twiddle factors for improved configurability. The designed architecture is further modified to perform variable point FFT targeted for application in multirate systems. The architecture designed is generic and can be implemented on any vendor platform.
在FPGA上实现可配置FFT的定制架构
傅里叶变换算法已经涵盖了多个工程领域,包括雷达、通信和图像处理系统等专业领域。因此,人们一直在努力提高FFT在实时系统和其他硬件中的实现效率。为了缩短设计时间和上市时间,FPGA供应商开发了可以在我们的应用中轻松使用的IP内核。但是这些IP核设计虽然效率很高,但却非常抽象,不能让设计者根据自己的需求进行修改,导致设计实现效率低下。供应商提供的IP内核不允许访问FFT内核矩阵,从而限制了使用它们的可配置性和效率。在本文中,我们设计了一个定制的体系结构来执行FFT,并访问旋转因子以提高可配置性。对所设计的体系结构进行了进一步的改进,以实现针对多速率系统应用的可变点FFT。所设计的体系结构是通用的,可以在任何供应商平台上实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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