G. Tsutsui, R. Bao, K. Lim, R. Robison, R. Vega, Jie Yang, Zuoguang Liu, Miaomiao Wang, O. Gluschenkov, C. Yeung, Koji Watanabe, S. Bentley, H. Niimi, Derrick Liu, Huimei Zhou, S. Siddiqui, Hoon Kim, R. Galatage, R. Venigalla, M. Raymond, P. Adusumilli, S. Mochizuki, T. Devarajan, Bruce Miao, Bei Liu, A. Greene, J. Shearer, P. Montanini, J. Strane, C. Prindle, E. Miller, J. Fronheiser, C. Niu, K. Chung, J. Kelly, H. Jagannathan, S. Kanakasabapathy, G. Karve, F. Lie, P. Oldiges, V. Narayanan, T. Hook, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare
{"title":"Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT","authors":"G. Tsutsui, R. Bao, K. Lim, R. Robison, R. Vega, Jie Yang, Zuoguang Liu, Miaomiao Wang, O. Gluschenkov, C. Yeung, Koji Watanabe, S. Bentley, H. Niimi, Derrick Liu, Huimei Zhou, S. Siddiqui, Hoon Kim, R. Galatage, R. Venigalla, M. Raymond, P. Adusumilli, S. Mochizuki, T. Devarajan, Bruce Miao, Bei Liu, A. Greene, J. Shearer, P. Montanini, J. Strane, C. Prindle, E. Miller, J. Fronheiser, C. Niu, K. Chung, J. Kelly, H. Jagannathan, S. Kanakasabapathy, G. Karve, F. Lie, P. Oldiges, V. Narayanan, T. Hook, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare","doi":"10.1109/IEDM.2016.7838439","DOIUrl":null,"url":null,"abstract":"Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2016.7838439","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.
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