A study of a10-bit 50MS/s low voltage low power pipelined ADC

Abstract

In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential solution for low-power high-speed applications, e.g., DVB-H, DVB-T and WLANs.