Building-in reliability, application to bipolar/CMOS/DMOS technology

Abstract

A permanent goal for an integrated circuit foundry is the improvement of reliability to avoid failures during component life. Ideally, the components should be tested in the mission profile conditions for the total duration. Specific tests must be accelerated to reduce the measurement time without creating new degradations, but also to detect the true defect or its origins. We have developed a building-in reliability approach for a front-end. The wafer level reliability (WLR) is set-up by electrical or physical tests during or at the end of the process, to eliminate defects directly at their origins. Our study concerned mainly a bipolar/CMOS/DMOS (BCD) technology.