Performance Analysis of Down Scaling Effect of Si based SRG Tunnel FET

Abstract

A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the 2D device simulator is used to examine the impact on the device parameters such as transconductance(gm) transconductancegeneration factor(TGF), intrinsic gain (gm/gds) output resistance (R0) unity gain cut-off frequency (fT) and Maximum Frequency of Oscillations (fmax) with respect to the continual downscaling of channel length for analog and RF performance.. Results shows that superior RF performance and poor analog performance were achieved as per th scaling down of gate length. Linearity FOM such as 1-dB compression point, VIP2, VIP3, IMD3 are explored to enquire the linearity performance of the proposed device. Hence, this work will be benificial for new generation of RF circuits needed for wireless communication systems and for system on chip applications.