M. Nakajima, T. Yamamoto, S. Ozaki, I. Sezaki, T. Kanakogi, T. Furuzono, T. Sakamoto, T. Aruga, M. Sumita, M. Tsutsumi, A. Ueda, T. Ichinomiya
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引用次数: 19
Abstract
A 32b RISC microprocessor core for Digital TV SoC occupies 14.8mm/sup 2/ in 0.13/spl mu/m CMOS with six Cu layers. The core runs at 400MHz with 500mW average dissipation at 1.35V. The integrated 4.0GB/s 3/spl times/4 cross-bar bus switch improves sustained system performance efficiency by 1.75 times.