Design and Implementation of a Modified Boost Topology with High Voltage Ratio and Efficiency Besides the Lower Semiconductors Stresses

Abstract

Article history: Received 07 November 2021 Received in revised form 25 April 2022 Accepted 08 May 2022 This paper has designed an upgraded form of the boost topology. The voltage ratio of the traditional step-up topology has been increased in quadratic form. Moreover, a low value of the duty cycle, number of components, and voltage/current stresses besides a high efficiency are bold features. The different parameters have been extracted for the ideal/non-ideal modes of the components and continuous/discontinuous current modes. In addition, the different features, such as the current/voltage stresses, have been compared. The efficiency of the designed topology has been extracted, and its various kind of power losses have been compared. The small-signal analysis has been done, and the bode diagram of the system has been extracted. Besides the increased voltage ratio of the designed topology compared to the traditional step-up converter, the continuity of the input current has remained a brilliant feature. Moreover, the semiconductors' stresses have been low-value compared to the recently proposed topologies. Moreover, higher efficiency besides higher voltage gain has been achieved. Finally, the experimental results have been compatible with the simulation and theoretical outcomes. The higher voltage gain of the proposed converter has been caused by the lower value of the duty cycle in comparison with the conventional boost converter, besides an acceptable efficiency and semiconductor stresses.