Concurrent use of two-dimensional process and device simulators in the development of a latch-up free BiCMOS process

Abstract

Use of two-dimensional process and device simulators in predicting the latch-up immunity of a BiCMOS process is described. Recent advances have resulted in the availability of a number of simulation tools such as PISCES in the device simulation area and others such as SUPRA and SUPREM-2, -3, and -4 in the process simulation area. SUPRA was used for process modeling, and PISCES-2B for device simulations. It is shown that despite SUPRA's limitations and restrictions in the sequential choice of process steps, with tricks and some help from one-dimensional SUPREM-3 results, satisfactory 2-D profiles can be obtained. Therefore, PISCES-2B receives a two-dimensional device structure with no manual interference. It is shown that the models developed yield not only the MOSFET characteristics but also the parasitic transistors gains. Results obtained from the simulation of the device under latch-up test conditions help the engineer to design latch-up-free CMOS and BiCMOS processes.<>