José Luis Saiz-Pérez, J. Pino, D. Mayor-Duarte, S. Khemchandani, Mario San Miguel-Montesdeoca, S. Mateos-Angulo
{"title":"Distributed power amplifier in GaN technology with tapered drain lines","authors":"José Luis Saiz-Pérez, J. Pino, D. Mayor-Duarte, S. Khemchandani, Mario San Miguel-Montesdeoca, S. Mateos-Angulo","doi":"10.1109/DCIS51330.2020.9268621","DOIUrl":null,"url":null,"abstract":"A Distributed Power Amplifier (DPA) with a tapered drain line is presented in this paper. The drain line impedance tapering technique allows to obtain a higher output power and efficiency compared to the conventional approach, whereas a constant drain line impedance avoids impedance changes in the power supply drive signal. The design was implemented using the D01GH/Si technology provided by the foundry OMMIC. The DPA achieves a Psat of 32 dBm and a flat gain over 14 dB in a frequency range that ranges from 1 to 8 GHz. Moreover, this circuit achieves a Power Added Efficiency (PAE) of 50%. Finally, the occupied area of the DPA is 2.2x1.2mm2 excluding pads.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS51330.2020.9268621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A Distributed Power Amplifier (DPA) with a tapered drain line is presented in this paper. The drain line impedance tapering technique allows to obtain a higher output power and efficiency compared to the conventional approach, whereas a constant drain line impedance avoids impedance changes in the power supply drive signal. The design was implemented using the D01GH/Si technology provided by the foundry OMMIC. The DPA achieves a Psat of 32 dBm and a flat gain over 14 dB in a frequency range that ranges from 1 to 8 GHz. Moreover, this circuit achieves a Power Added Efficiency (PAE) of 50%. Finally, the occupied area of the DPA is 2.2x1.2mm2 excluding pads.