Implementation Of An Efficient All Digital Phase Locked Loop

Abstract

The creation of an efficient All Digital Phase Locked Loop is demonstrated in this study (ADPLL).The work is initiated to analyze the ways in which the components of an ADPLL network could be designed from the pool. The proposed ADPLL network is chosen in such a way to improve its efficiency from that of previous studies. The Design is modeled using VERILOG Hardware Description language (HDL) and analyzed using Xilinx ISE 9.1,spartan3 family,XC3S4000L.At last the efficiency of the design is analyzed from the previous works by considering various parameters