Automatic executable code generation for DNN accelerator ReNA

Abstract

We have been developing ReNA as a DNN accelerator for the edge, which is controlled by directly specifying control signals for each circuit by microcode instructions. The current control method is not efficient because of its low readability and manual generation of execution code. In addition, it requires a large amount of instructions and large SRAM size to store the control signals. In this paper, we try to solve this problem by abstracting the microcode instructions and reducing the amount of instructions. We also improve efficiency of model implementation by enabling automatic generation of the microcode. As a result, we were able to reduce the required SRAM capacity by about 86% and halve the area of the SRAM for storing instructions.