Evaluation of multi-layered gate design on GME-TRC MOSFET for wireless applications

Abstract

In this paper, the impact of multi-layered gate design assimilation on Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET has been studied for wireless applications in terms of linearity performance metrics, using device simulators: ATLAS and DEVEDIT, and compared with conventional Trapezoidal Recessed channel (TRC) and GME-TRC MOSFETs. Simulation study reveals that GME-TRC MOSFET with Multi-Layered Gate implementation significantly enhances the linearity performance in comparison with conventional TRC-MOSFET and GME-TRC MOSFET in terms of figure of merit (FOM) metrics: VIP2, VIP3, IIP3 and higher order transconductance coefficients: gm1, gm2, gm3, thus proving its efficacy for high performance wireless applications.