{"title":"Processor configuration for real-time SAR image generation","authors":"T. H. Einstein","doi":"10.1109/NRC.1998.677979","DOIUrl":null,"url":null,"abstract":"This paper describes how to configure a multicomputer for real-time SAR image generation so as to minimize either the total number of processors or the amount of data buffer memory required. The total number of processors is minimized by arranging the processors in a pipeline of parallel processor clusters, with double-buffering at the input and output of each cluster. In contrast, the total memory requirement is minimized by implementing the application on a round-robin arrangement of identical processor modules, each module consisting of a single cluster of parallel processors. Depending upon the incoming data rate to be processed, the memory requirement of this minimum-memory configuration may be as little as one-eighth that of the minimum-processor pipeline configuration, at the cost of between 25 and 70% more processors.","PeriodicalId":432418,"journal":{"name":"Proceedings of the 1998 IEEE Radar Conference, RADARCON'98. Challenges in Radar Systems and Solutions (Cat. No.98CH36197)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1998 IEEE Radar Conference, RADARCON'98. Challenges in Radar Systems and Solutions (Cat. No.98CH36197)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRC.1998.677979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes how to configure a multicomputer for real-time SAR image generation so as to minimize either the total number of processors or the amount of data buffer memory required. The total number of processors is minimized by arranging the processors in a pipeline of parallel processor clusters, with double-buffering at the input and output of each cluster. In contrast, the total memory requirement is minimized by implementing the application on a round-robin arrangement of identical processor modules, each module consisting of a single cluster of parallel processors. Depending upon the incoming data rate to be processed, the memory requirement of this minimum-memory configuration may be as little as one-eighth that of the minimum-processor pipeline configuration, at the cost of between 25 and 70% more processors.