I. Bahl, R. Wang, A. Geissberger, E. Griffin, C. Andricos
{"title":"C-band 10 Watt MMIC amplifier manufactured using refractory SAG process","authors":"I. Bahl, R. Wang, A. Geissberger, E. Griffin, C. Andricos","doi":"10.1109/MCS.1989.37254","DOIUrl":null,"url":null,"abstract":"The design and performance of a C-band single-chip GaAs monolithic microwave integrated circuit (MMIC) amplifier manufactured using a fully planar, refractory, self-aligned gate (SAG) technology is described. The design uses a 4-mm gate periphery FET with a unit finger width of 250 mu m as a standard cell. The power MMIC design is based on measured data for the FET, which has three source vias for low parasitic source grounding. The FET was optimized for maximum power and efficiency at C-band and has 16 fingers. The design uses an innovative method to determine accurate linear models for the power FET used to design the matching network and for simulating accurately the performance of the power amplifier. The amplifier demonstrates 10 W power output at 5.5 GHz with associated gain of 5 dB and power-added efficiency of 36%. The functional yield of the IC on the best wafer was 70%.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCS.1989.37254","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The design and performance of a C-band single-chip GaAs monolithic microwave integrated circuit (MMIC) amplifier manufactured using a fully planar, refractory, self-aligned gate (SAG) technology is described. The design uses a 4-mm gate periphery FET with a unit finger width of 250 mu m as a standard cell. The power MMIC design is based on measured data for the FET, which has three source vias for low parasitic source grounding. The FET was optimized for maximum power and efficiency at C-band and has 16 fingers. The design uses an innovative method to determine accurate linear models for the power FET used to design the matching network and for simulating accurately the performance of the power amplifier. The amplifier demonstrates 10 W power output at 5.5 GHz with associated gain of 5 dB and power-added efficiency of 36%. The functional yield of the IC on the best wafer was 70%.<>